Encoding:

Format:

ADDUH[_R].QB 

ADDUH.QB     rd, rs, rt

ADDUH_R.QB   rd, rs, rt

Purpose:

Unsigned Add Vector Quad-Bytes And Right Shift to Halve Results

Element-wise unsigned addition of un signed byte vectors, with right shift by one bit to halve each result, with optional rounding.

Description:

rd = round((rs31..24 + rt31..24)>>1) || round((rs23..16 + rt23..16)>>1) ||round((rs15..8 + rt15..8)>>1) || round((rs7..0 + rt7..0)>>1)

Each element from the four unsigned byte values in register rs is added to the corresponding unsigned byte element in register rt to create an unsigned interim result.

In the non-rounding instruction variant, each interim result is then shifted right by one bit before being written to the corresponding unsigned byte element of destination register rd.

In the rounding version of the instructi on, a value of 1 is added at the least- significant bit position of each interim result before being right-shifted by one bit and written to the destination register.

This instruction does not modify the DSPControl register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

ADDUH.QB:
   tempD7..0 = rightShift1AddU8( GPR[rs]31..24 , GPR[rt]31..24 )
   tempC7..0 = rightShift1AddU8( GPR[rs]23..16 , GPR[rt]23..16 )
   tempB7..0 = rightShift1AddU8( GPR[rs]15..8 , GPR[rt]15..8 )
   tempA7..0 = rightShift1AddU8( GPR[rs]7..0 , GPR[rt]7..0 )
   GPR[rd]63..0 = (tempD7)32 || tempD7..0 || tempC7..0 || tempB7..0 || tempA7..0
ADDUH_R.QB:
   tempD7..0 = roundRightShift1AddU8( GPR[rs]31..24 , GPR[rt]31..24 )
   tempC7..0 = roundRightShift1AddU8( GPR[rs]23..16 , GPR[rt]23..16 )
   tempB7..0 = roundRightShift1AddU8( GPR[rs]15..8 , GPR[rt]15..8 )
   tempA7..0 = roundRightShift1AddU8( GPR[rs]7..0 , GPR[rt]7..0 )
   GPR[rd]63..0 = (tempD7)32 || tempD7..0 || tempC7..0 || tempB7..0 || tempA7..0
function rightShift1AddU8( a7..0 , b7..0 )
   temp8..0 = (( 0 || a7..0 ) + ( 0 || b7..0 ))
   return temp8..1
endfunction rightShift1AddU8
function roundRightShift1AddU8( a7..0 , b7..0 )
   temp8..0 = (( 0 || a7..0 ) + ( 0 || b7..0 ))
   temp8..0 = temp8..0 + 1
   return temp8..1
endfunction roundRightShift1AddU8

Exceptions:

Reserved Instruction, DSP Disabled